In machine vision applications, it is common to acquire image data related to the surface of a workpiece and to store this data for further processing. Stored image data is used for pattern-recognition, error detection and other surface inspection applications. FIG. 1 details a basic image processing arrangement according to the prior art. A camera 30 having a lens 32 for acquiring an image and an electro-optical pickup device, such as a CCD array 34, transmits image data over a data line 36 to a memory device 38. The memory device in this example comprises a random access memory (RAM) configured to receive image data. Data is typically provided in digital form, often following conversion from an analog form by a analog to digital converter (not shown) located in the data path between the CCD array and the image RAM 38. Image data is stored in the image RAM 38 as individual pixels that each represent a given segment of the overall image. Each pixel represents a relatively small part of the total image, such that in aggregate, the image appears relatively continuous. Each pixel has a discrete intensity value that defines a brightness and, when applicable, a shade of color. Where the image is acquired and recorded in color, a pixel may be formed from at least three different-color sub-pixels that form the overall color shade. Alternatively, where the image is monochromatic, a numerical grayscale intensity value is recorded for the pixel. As described further below, the RAM is organized as a series of rows and columns, each individually addressed by an incoming data line. By addressing the appropriate row and column, all or part of a particular pixel intensity value can be accessed and read. An image processor 40 that can comprise any acceptable microprocessor or application specific integrated circuit (ASIC) retrieves intensity values as data over a multi-bit data line 42 based upon input pixel addresses transmitted over a multi-bit address line 44. Model or "template" image data, representative of an image to be compared to the acquired image, can be input to the processor through a variety of input lines denoted generally as the input line 48. The processor matches the model data to the acquired data stored in the RAM 38. The processor, using known techniques, calculates an overall match of the acquired data with the known data by combining the results of each individual pixel-by-pixel match performed by the processor. Results of matches made by the processor are output on an output line 50 to other processors or computers. These processors utilize the output data to perform more advanced operations such as overall pattern recognition.
In another example, the processor can acquire several pixels over the RAM data line 42 that are adjacent each other and, based upon these adjacent pixels, derive modified pixel values (such as average values for all pixels in a group) that are output on the output line 50. These values can be returned through a return line 52 (shown in phantom) to the RAM 38 for restorage. Appropriate addressing functions provided by the processor 40 can facilitate storage of the modified pixel values in the appropriate locations in the RAM.
The image processing arrangement of FIG. 1 enables pixel data to be accessed in the RAM in a largely serial manner. That is, only one pixel data can be read from the RAM to the processor in each addressing cycle. Some microprocessor arrangements such as the well-known Pentium.RTM. MMX.RTM. microprocessor available from Intel Corp. can access several pixel data simultaneously. For example the forenamed microprocessor uses a single address to access eight sequential eight-bit pixel data in one clock cycle. However, this arrangement has a limitation in that it requires all pixels data to be stored adjacent to each other in the RAM. Hence, to process a group of pixels widely spaced in two dimensions of an image, or at remote spacings from each other, the processor must address pixel data over several clock cycles. This slows the image processing procedure. Speed is a concern in a high-speed machine vision environment in which a large volume of data must be managed by the processing system continuously.
It is, therefore, an object of this invention to provide a more efficient method and apparatus for accessing multiple pixels in an image processing memory array using a reduced number of memories.